Implementation of DES Algorithm Using FPGA Technology

The goal was to build two architectures: one fast (with the highest throughput possible) and one small (the less area as possible), given a pipelined non-optimized architecture.

To achieve this, I used Modelsim to simulate, FPGA compiler II and Leonardo to synthesize, and Xilinx ISE to place & route. The FPGA used was a Spartan II.

If you are interested, I give you here the report in pdf and the vhdl files:

• Report (pdf, 2.12 mb)
• files (zip, 49 kb)

Since the pdf report is huge, I advise you to download it using right click and "save target as...".

For all questions and remarks, feel free to send me an e-mail.